An IDDQ Fault Model to Facilitate the Design of Built-In Current Sensor (BICSs)

Unfortunately there are some problems in deIn this paper, we present a n e f i c i e n t and accurate’ IDDQ faul t modeling technique f o r digital CMOS circuit. Both, the normal and faul ty “current” behaviors of a CMOS digital circuit can be described by th i s model. Also the parasit ic capacitive and induct ive parameters can be emulaled. A f o r m a l method f o r creating this model f r o m any g iven CMOS circuit is outlined. Using th i s model , circuit design of builtin current sensors (BICSs) can be designed and vaC idated without introducing the actual circxit under t e s t (CUT) which implanted a fau l t . Exper imenta l data f o r the application t o the design of BICSs is also given.